default:
	verilator \
	-exe \
	-O3 \
	--cc \
	--top-module SimTop \
	sim_main.cpp \
	Sim.sv AXI_BUS.sv \
	-I./rtl \
	-I./verilog-axi/rtl \
	--no-timing  \
	--max-num-width 150000 \
	-j 8 \
	--trace \
	-Wno-STMTDLY -Wno-WIDTH -Wno-UNUSEDSIGNAL  -Wno-SYNCASYNCNET -Wno-CASEINCOMPLETE -Wno-INFINITELOOP -Wno-TIMESCALEMOD -Wno-PINCONNECTEMPTY -Wno-EOFNEWLINE -Wno-DECLFILENAME 

compile:
	make -C obj_dir -f VSimTop.mk VSimTop
